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WM8983 Datasheet(PDF) 21 Page - Cirrus Logic |
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WM8983 Datasheet(HTML) 21 Page - Cirrus Logic |
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21 / 129 page  WM8983 Rev 4.6 21 CONTROL INTERFACE TIMING – 3-WIRE MODE 3-wire mode is selected by connecting the MODE pin high. CSB/GPIO SCLK SDIN t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 8 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25 oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 80 ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL 80 ns SCLK pulse width high tSCH 80 ns SDIN to SCLK set-up time tDSU 40 ns SCLK to SDIN hold time tDHO 40 ns CSB pulse width low tCSL 40 ns CSB pulse width high tCSH 40 ns CSB rising to SCLK rising tCSS 40 ns Pulse width of spikes that will be suppressed tps 0 5 ns |
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