Data Sheet

AD8330

Rev. H | Page 7 of 32

1

S

O

P

V

T

S

F

O

16

2

R

T

N

C

L

B

N

E

15

3

O

S

P

V

I

S

P

V

14

4

I

H

P

O

I

H

N

I

13

5

O

L

P

O

O

L

N

I

12

6

P

O

M

C

E

D

O

M

11

7

G

A

M

V

S

B

D

V

10

8

M

M

O

C

N

G

M

C

9

AD8330

TOP VIEW

(Not to Scale)

Figure 3. 16-Lead QSOP Pin Configuration

Table 4. 16-Lead QSOP Pin Function Descriptions

Pin No.

Mnemonic

Description

1

OFST

Internal Offset Compensation Feature. When the OFST pin is unconnected, this feature is enabled.

When the OFST pin is grounded, this feature is disabled. See the Offset Compensation section.

2

ENBL

Power Enable, Active High.

3

VPSI

Positive Supply for Input Stages.

4

INHI

Differential Signal Input, Positive Polarity.

5

INLO

Differential Signal Input, Negative Polarity.

6

MODE

7

VDBS

8

CMGN

Common Baseline for Gain Control Interfaces.

9

COMM

Ground for Input and Gain Control Bias Circuitry.

10

VMAG

11

CMOP

Ground for Output Stages.

12

OPLO

Differential Signal Output, Negative Polarity.

13

OPHI

Differential Signal Output, Positive Polarity.

14

VPSO

Positive Supply for Output Stages.

15

CNTR

Common-Mode Output Voltage Control.

16

VPOS

Positive Supply for Inner Stages.