 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
X98021 Datasheet(PDF) 7 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
X98021 Datasheet(HTML) 7 Page - Renesas Technology Corp |
|
|
7 / 29 page  X98021 FN8219 Rev 3.00 Page 7 of 29 March 8, 2006 t HSYNCin-to-HSout = 7.5ns + (PHASE/64 +10.5)*tPIXEL D 1 D 3 Programmable Width and Polarity Analog Video In P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 0 P 9 D 0 R P/GP/BP[7:0] HS OUT P 10 P 11 P 12 D 2 The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE’s output signals DATACLK R S/GS/BS[7:0] HSYNC IN FIGURE 5. 48 BIT OUTPUT MODE Programmable Width and Polarity Analog Video In P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 0 P 9 HS OUT P 10 P 11 The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE’s output signals DATACLK HSYNC IN D 0 R P/GP/BP[7:0] D 2 D 1 R S/GS/BS[7:0] t HSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
