DLPC3470 datasheet(6/70 Pages) TI1

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DLPC3470

DLPS110 – APRIL 2018

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Pin Functions – Board Level Test, Debug, and Initialization (continued)

I/O

DESCRIPTION

NAME

NUMBER

TSTPT_1

R13

Test pin 1 (includes weak internal pulldown) tri-stated while RESETZ is asserted low. Sampled

as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and

then driven as an output.

Normal use: reserved for test output. Should be left open for normal use.

Note: Do not apply and external pullup to this pin to avoid DLPC3470 controller operation in test

mode operation.

TSTPT_2

R14

Test pin 2 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Normal use: reserved for test output. Should be left open for normal use.

Note: Do not apply and external pullup to this pin to avoid DLPC3470 controller operation in test

mode.

TSTPT_3

R15

Test pin 3 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Reserved for test output. Maintain this pin in open status for normal use.

TSTPT_4

P14

Test pin 4 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Reserved for TRIG_OUT_1 signal (Output).

TSTPT_5

P15

Test pin 5 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Reserved for test output. Maintain this pin in open status for normal use.

TSTPT_6

N14

Test pin 6 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Reserved for test output. Maintain this pin in open status for normal use.

No alternative use: Do not allow external logic to unintentionally pull this pin high to avoid

DLPC3470 controller operation in test mode.

TSTPT_7

N15

Test pin 7 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Reserved for test output. Maintain this pin in open status for normal use.

DLPC3470 Datasheet(PDF) 6 Page - Texas Instruments

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