3

dc2520af

DEMO MANUAL DC2520A

DC2520A SETUP

+

–

+

–

AIN0

R107

49.9

U25B

LT6237IDD

U25A

LT6237IDD

C96

0.1µF

C94

1000pF

C98

OPT

C116

OPT

R129

1k

R108

24.9

R123

24.9

C104

0.1µF

R124

49.9

C100

39pF

C112

39pF

EN

C102

1000pF

dc2326 F02

R113

0

R119

1k

DC Power

TheDC2520Arequires±9VDCanddraws+132mA/–52mA.

Most of the supply current is consumed by the FPGA,

opamps, regulators and discrete logic on the board. The

±9VDC input voltage powers the ADC through LT1763

regulators which provide protection against accidental

reverse bias. Additional regulators provide power for the

FPGA and opamps.

Clock Source

to the clock input, J1. The clock input is AC coupled so the

DC level of the clock signal is not important. A generator

such as the Rohde & Schwarz SMB100A high speed clock

source is recommended to drive the clock input. Even a

good generator can start to produce noticeable jitter at

low frequencies. Therefore it is recommended for lower

sample rates to divide down a higher frequency clock to

the desired sample rate. The ratio of clock frequency to

conversion rate is shown in the Assembly Options table. If

theclockinputistobedrivenwithlogic,itisrecommended

that the 49.9Ω termination resistor (R4) be removed.

Driving R4 with discrete logic may result in slow rising

edges. These slow rising edges may compromise the SNR

of the converter in the presence of high-amplitude higher

frequency input signals.

Data Output

Parallel data output from this board (0V to 2.5V default),

if not connected to the DC890, can be acquired by a logic

analyzer,andsubsequentlyimportedintoaspreadsheet,or

mathematical package depending on what form of digital

signal processing is desired. Alternatively, the data can

be fed directly into an application circuit. Use pin 50 of

P1 to latch the data. The data should be latched using the

negative edge of this signal. The data output signal levels

at P1 can also be increased to 0V-3.3V if the application

circuit requires a higher voltage. This is accomplished by

moving JP2 to the 3.3V position.

Figure 2. 0V–4.096V Single-Ended to Fully Differential DC Coupled Driver