Start/Stop

Logic

Slave Address

Comparator

Word Address

Pointer

Row

decoder

EEPROM

Cell Array

256 x 8 bits

HV Generation

Timing Control

Control Logic

Column Decoder

Data Register

SCL

WP

SDA

A0

A1

A2

Figure 1-1.

24LLC02 Block Diagram

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Email: server@ceramate.com.tw

Tel:886-3-3529445

Http: www.ceramate.com.tw

Fax:886-3-3521052

Page

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Rev 1.2 May 6,2002

24LLC02

2K-bit Serial EEPROM for Low Power