LTC2435-1IGN datasheet(14/40 Pages) LINER

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LTC2435/LTC2435-1

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APPLICATIO S I FOR ATIO

Output Data Format

The LTC2435/LTC2435-1 serial output data stream is 24

bits long. The first 3 bits represent status information

indicating the sign and conversion state. The next 21 bits

are the conversion result, MSB first. The third and fourth

bit together are also used to indicate an underrange

condition (the differential input voltage is below –FS) or an

overrange condition (the differential input voltage is above

+FS).

Bit 23 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 22 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 21 (third output bit) is the conversion result sign indi-

cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this

bit is LOW.

Bit 20 (fourth output bit) is the most significant bit (MSB)

of the result. This bit in conjunction with Bit 21 also

provides the underrange or overrange indication. If both

Bit 21 and Bit 20 are HIGH, the differential input voltage is

above +FS. If both are LOW, the differential input voltage

is below –FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2435/LTC2435-1 Status Bits

Bit 23

Bit 22 Bit 21 Bit 20

Input Range

EOC

DMY

SIG

MSB

VIN ≥ 0.5 • VREF

0V ≤ VIN < 0.5 • VREF

–0.5 • VREF ≤ VIN < 0V

VIN < – 0.5 • VREF

Bits 20-0 are the 21-bit conversion result MSB first.

Bit 0 is the least significant bit (LSB).

Data is shifted out of the SDO pin under control of the serial

clock (SCK), see Figure 3. Whenever CS is HIGH, SDO

remains high impedance and any externally generated

SCK clock pulses are ignored by the internal data out shift

In order to shift the conversion result out of the device, CS

must first be driven LOW. EOC is seen at the SDO pin of the

device once CS is pulled LOW. EOC changes real time from

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external

microcontroller. Bit 23 (EOC) can be captured on the first

rising edge of SCK. Bit 22 is shifted out of the device on the

first falling edge of SCK. The final data bit (Bit 0) is shifted

out on the falling edge of the 23rd SCK and may be latched

on the rising edge of the 24th SCK pulse. On the falling

edge of the 24th SCK pulse, SDO goes HIGH indicating the

initiation of a new conversion cycle. This bit serves as EOC

(Bit 23) for the next conversion cycle. Table 2 summarizes

the output data format.

As long as the voltage on the IN+ and IN– pins is maintained

within the – 0.3V to (VCC + 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage VIN from –FS = –0.5 • VREF to

+FS = 0.5 • VREF. For differential input voltages greater

than +FS, the conversion result is clamped to the value

corresponding to the +FS. For differential input voltages

below –FS, the conversion result is clamped to the value

corresponding to –FS – 1LSB.

Offset Accuracy and Drift

Unlike the LTC2430 and most of the LTC2400 family, the

LTC2435/LTC2435-1 do not perform an offset calibration

every cycle. The reason for this is to increase the data output

rate while maintaining line frequency rejection.

While the initial accuracy of the LTC2435/LTC2435-1

offset is within 5mV (see Figure 4), several unique prop-

erties of the LTC2435/LTC2435-1 architecture nearly elimi-

nate the drift of the offset error with respect to temperature

and supply.

As shown in Figure 5, the offset variation with temperature

is less than 3ppm over the complete temperature range of

–50°C to 100°C. This corresponds to a temperature drift

of 0.022ppm/°C.

While the variation in offset with supply voltage is propor-

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