AD8285CP-EBZ datasheet(7/28 Pages) AD

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AD8285

Data Sheet

Rev. B | Page 6 of 27

SWITCHING SPECIFICATIONS

AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI =

DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain =

34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted.

Table 4.

Parameter2

Temperature

Min

Typ

Max

Unit

CLOCK

Clock Rate

Full

MSPS

Clock Pulse Width High (tEH) at 72 MSPS

Full

6.94

Clock Pulse Width Low (tEL) at 72 MSPS

Full

6.94

Clock Pulse Width High (tEH) at 40 MSPS

Full

12.5

Clock Pulse Width Low (tEL) at 40 MSPS

Full

12.5

OUTPUT PARAMETERS

Propagation Delay (tPD) at 72 MSPS

Full

1.5

2.5

5.0

Rise Time (tR)3

Full

1.9

Fall Time (tF)3

Full

1.2

Data Set-Up Time (tDS) at 72 MSPS

Full

9.0

10.0

11.0

Data Hold Time (tDH) at 72 MSPS

Full

1.5

4.0

5.0

Data Set-Up Time (tDS) at 40 MSPS

Full

21.5

22.5

23.5

Data Hold Time (tDH) at 40 MSPS

Full

1.5

4.0

5.0

Pipeline Latency

Full

Clock cycles

1 x stands for A, B, C, or D.

2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions, and how these tests were completed.

3 Not shown in Figure 2.

Figure 2. Timing Definitions for Switching Specifications

N –1

INAx

N – 7

N – 6

N – 5

N – 4

N – 3

N – 2

N – 1

CLK–

CLK+

D[11:0]

tPD

tEH

tEL

tDS

tDH

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