AD7712_17 datasheet(18/29 Pages) AD

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REV. F

AD7712

–17–

VBIAS Input

The VBIAS input determines at what voltage the internal analog

circuitry is biased. It essentially provides the return path for

analog currents flowing in the modulator, and as such it should

be driven from a low impedance point to minimize errors.

For maximum internal headroom, the VBIAS voltage should be

set halfway between AVDD and VSS. The difference between

AVDD and (VBIAS + 0.85

VREF) determines the amount of

headroom the circuit has at the upper end, while the difference

between VSS and (VBIAS – 0.85

VREF) determines the amount

of headroom the circuit has at the lower end. Care should be

taken in choosing a VBIAS voltage to ensure that it stays within

prescribed limits. For single +5 V operation, the selected VBIAS

voltage must ensure that VBIAS

± 0.85

VREF does not exceed

AVDD or VSS or that the VBIAS voltage itself is greater than

VSS + 2.1 V and less than AVDD – 2.1 V. For single +10 V

operation or dual

±5 V operation, the selected VBIAS voltage

must ensure that VBIAS

± 0.85

VREF does not exceed AVDD

or VSS or that the VBIAS voltage itself is greater than VSS + 3 V

or less than AVDD – 3 V. For example, with AVDD = +4.75 V,

VSS = 0 V and VREF = +2.5 V, the allowable range for the VBIAS

voltage is +2.125 V to +2.625 V. With AVDD = +9.5 V, VSS = 0 V

and VREF = +5 V, the range for VBIAS is +4.25 V to +5.25 V.

With AVDD = +4.75 V, VSS = –4.75 V, and VREF = +2.5 V, the

VBIAS range is –2.625 V to +2.625 V.

The VBIAS voltage does have an effect on the AVDD power supply

rejection performance of the AD7712. If the VBIAS voltage tracks

the AVDD supply, it improves the power supply rejection from

the AVDD supply line from 80 dB to 95 dB. Using an external

Zener diode connected between the AVDD line and VBIAS as the

source for the VBIAS voltage gives the improvement in AVDD

power supply rejection performance.

USING THE AD7712

SYSTEM DESIGN CONSIDERATIONS

The AD7712 operates differently from successive approximation

ADCs or integrating ADCs. Since it samples the signal continu-

ously, like a tracking ADC, there is no need for a start convert

command. The output register is updated at a rate determined

by the first notch of the filter, and the output can be read at any

time, either synchronously or asynchronously.

Clocking

The AD7712 requires a master clock input, which may be an

external TTL/CMOS compatible clock signal applied to the

MCLK IN pin with the MCLK OUT pin left unconnected.

Alternatively, a crystal of the correct frequency can be connected

between MCLK IN and MCLK OUT, in which case the clock

circuit will function as a crystal controlled oscillator. For lower

clock frequencies, a ceramic resonator may be used instead of

the crystal. For these lower frequency oscillators, external

capacitors may be required on either the ceramic resonator or

on the crystal.

The input sampling frequency, the modulator sampling frequency,

the –3 dB frequency, the output update rate, and the calibration

time are all directly related to the master clock frequency, fCLK

IN. Reducing the master clock frequency by a factor of 2 will

halve the above frequencies and update rate and will double

the calibration time.

The current drawn from the DVDD power supply is also directly

related to fCLK IN. Reducing fCLK IN by a factor of 2 will halve the

DVDD current but will not affect the current drawn from the

AVDD power supply.

System Synchronization

If multiple AD7712s are operated from a common master clock,

they can be synchronized to update their output registers simul-

taneously. A falling edge on the

SYNC input resets the filter

and places the AD7712 into a consistent, known state. A com-

mon signal to the AD7712’s

SYNC inputs will synchronize their

operation. This would normally be done after each AD7712 has

performed its own calibration or has had calibration coefficients

loaded to it.

The

SYNC input can also be used to reset the digital filter in

systems where the turn-on time of the digital power supply

(DVDD) is very long. In such cases, the AD7712 will start oper-

ating internally before the DVDD line has reached its minimum

operating level, 4.75 V. With a low DVDD voltage, the AD7712’s

internal digital filter logic does not operate correctly. Thus, the

AD7712 may have clocked itself into an incorrect operating

condition by the time that DVDD has reached its correct level.

The digital filter will be reset upon issue of a calibration

command (whether it is self-calibration, system calibration, or

background calibration) to the AD7712. This ensures correct

operation of the AD7712. In systems where the power-on

default conditions of the AD7712 are acceptable, and no calibra-

tion is performed after power-on, issuing a

SYNC pulse to the

AD7712 will reset the AD7712’s digital filter logic. An R, C on

the

SYNC line, with R, C time constant longer than the DV

power-on time, will perform the

SYNC function.

Accuracy

Sigma-delta ADCs, like VFCs and other integrating ADCs, do

not contain any source of nonmonotonicity and inherently offer

no missing codes performance. The AD7712 achieves excellent

linearity by the use of high quality, on-chip silicon dioxide

capacitors, which have a very low capacitance/voltage coefficient.

The device also achieves low input drift through the use of chop-

per stabilized techniques in its input stage. To ensure excellent

performance over time and temperature, the AD7712 uses digital

calibration techniques that minimize offset and gain error.

Autocalibration

Autocalibration on the AD7712 removes offset and gain errors

from the device. A calibration routine should be initiated on the

device whenever there is a change in the ambient operating

temperature or supply voltage. It should also be initiated if there

is a change in the selected gain, filter notch, or bipolar/unipolar

input range. However, if the AD7712 is in its background cali-

bration mode, the above changes are all automatically taken

care of (after the settling time of the filter has been allowed for).

The AD7712 offers self-calibration, system calibration, and

background calibration facilities. For calibration to occur on the

selected channel, the on-chip microcontroller must record the

modulator output for two different input conditions. These are

zero-scale and full-scale points. With these readings, the micro-

controller can calculate the gain slope for the input to output

transfer function of the converter. Internally, the part works

with a resolution of 33 bits to determine its conversion result of

either 16 bits or 24 bits.

AD7712 Datasheet(PDF) 18 Page - Analog Devices

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