The MCM69F737 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 128K words of 36 bits each. This device integrates input registers, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

• MCM69F737–7.5: 7.5 ns Access/8.5 ns Cycle (117 MHz)
    MCM69F737–8: 8 ns Access/10 ns Cycle (100 MHz)
    MCM69F737–8.5: 8.5 ns Access/11ns Cycle (90 MHz)
    MCM69F737–11: 11 ns Access/20 ns Cycle (50 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages