Description
CD4095BMS and CD4096BMS are J-K Master-Slave FlipFlops featuring separate AND gating of multiple J and K inputs. The gated J-K inputs control transfer of information into the master section during clocked operation. Information on the J-K inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse. SET and RESET inputs (active high) are provided for asynchronous operation.

Features
• Set-Reset Capability
• High Voltage Types (20V Rating)
• CD4095BMS Non-Inverting J and K Inputs
• CD4096BMS Inverting and Non-Inverting J and K Inputs
• 16MHz Toggle Rate (Typ.) at VDD - VSS = 10V
• Gated Inputs
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
    - 1V at VDD = 5V
    - 2V at VDD = 10V
    - 2.5V at VDD = 15V
• Meets all requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications
• Registers
• Counters
• Control Circuits