DESCRIPTION

The Hynix HY5DV641622 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth.

FEATURES

•3.3V for VDDand 2.5V for VDDQpower supply

• All inputs and outputs are compatible with SSTL_2 interface

• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)

• x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O

• Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)

• Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe

• All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock

• Write mask byte controls by LDM and UDM

• Programmable /CAS Latency 3 / 4 supported

• Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode

• Internal 4 bank operations with single pulsed /RAS

• tRAS Lock-Out function supported

• Auto refresh and self refresh supported

• 4096 refresh cycles / 64ms

• Full, Half and Matched Impedance(Weak) strength driver option controlled by EMRS