INTRODUCTION
The Video Decoder and System Controller with JTAG (VDSC/JTAG) is a CMOS device integrating a 680X0 family system controller and video graphics decoder, see Figure 1–1 below.
The MCD212 is a programmable, multi–scan video device that can function as either a master or a slave. It is functionally equivalent to the MCD211 with the addition of JTAG testing. The MCD212 is a drop–in replacement for the MCD211 if the JTAG functionality is not required. It can directly drive up to 5M bytes1 of memory and provides chip–select signals for system ROM and peripherals. The on–chip DRAM controller can support up to 4M bytes DRAM and controls access to the unspecialized System or Video DRAM. The CPU can access any memory location, even during active video display lines, thereby boosting system performance.

FEATURES
System Interface:
• Direct Interface for 680X0 Bus Compatible Devices
• 1M Byte ROM Control
• 1K Byte I/O Control
• Reset Sequencer, Including ROM Shadowing
• Watchdog Timer

DRAM Interface:
• 4M Byte DRAM Direct Drive
• 256K x 4, 1M x 4, and 256K x 16 DRAM Types Can be Used

Video Interface:
• Up to 768 x 560 Screen Resolution
• Capability to Display Run–length Coded Files
• Mosaic Effect
• 256–entry Color Look Up Table (CLUT)
• Two Delta YUV Decoders
• Cursor Shape, Color, and Blink Control
• Overlaying of Four Video Planes
• Special Effects via Weight Control, Priority Control, etc.
• Dynamic Programmable Registers and CLUT Reload in Retrace Period
• Digital RGB Output (8 Bits per Component)
• Synchro Generator for 50 and 60 Hz Scan
• Synchronization with External Video

General:
• CMOS Technology
• 160–pin Quad Flat Pack Plastic Package