Description
The TC551001BPL is a 1,048,576 bits static random access memory organized as 131,072 words by 8 bits using CMOS technology, and operated from a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating current of 5mA/MHz (typ.) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low power standby mode in which the standby current is 2 µ A typically. The TC551001BPL has three control inputs. Chip Enable inputs (CE1, CE2) allow for device selection and data retention control, while an Output Enable input (OE) provides fast memory access. The TC551001BPL is suitable for use in microprocessor application systems where high speed, low power, and battery backup are required. The TC551001BPL is offered in a standard dual-in-line 32-pin plastic package, a small outline plastic package, and a thin small outline plastic package (forward, reverse type).

Features
■ Low power dissipation :
■ 27.5mW/MHz (typ.)
■ Standby current: 4 µ A (max.) at Ta = 25 °
■ C
■ 5V single power supply
■ Access time (max.)
■ Power down feature:
■ CE1, CE2
■ Data retention supply voltage:
■ 2.0 ~ 5.5V
■ Inputs and outputs directly TTL compatible
■ Package TC551001BPL : DIP32-P-600 TC551001BFL : SOP32-P-525 TC551001BFTL : TSOP32-P-0820 TC551001BTRL : TSOP32-P-0820A TC551001BPL/BFL/BFTL/BTRL -70L -85L Access Time 70ns 85ns CE1 Access Time 70ns 85ns CE2 Access Time 70ns 85ns OE Access Time 35ns 45ns