▪ SMBus write lock feature; increases system security
▪ 2 software-configurable input-to-output delay lines; manage
transport delay for complex topologies
▪ LP-HCSL outputs; eliminate 24 resistors, save 41mm2 of area (1233E)
▪ LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save
82mm2 of area (1253E)
▪ 12 OE# pins; hardware control of each output
▪ 3 selectable SMBus addresses; multiple devices can share same SMBus segment
▪ Selectable PLL bandwidths; minimizes jitter peaking in
cascaded PLL topologies
▪ Hardware/SMBus control of PLL bandwidth and bypass;
change mode without power cycle
▪ Spread spectrum compatible; tracks spreading input clock for
EMI reduction
▪ 100MHz PLL Mode; UPI support
▪ 10 x 10 mm 72-VFQFPN package; small board footprint