▪ Integrated terminations for 100Ω and 85Ω systems
save 4 resistors per output
▪ 112–206 mW typical power consumption (at 3.3V)
▪ VDDIO rail allows 35% power savings at optional
1.05V (9FGL06 and 9FGL08 only)
▪ Devices contain default configuration; SMBus not required
▪ SMBus-selectable features allows optimization to
customer requirements:
• Input polarity and pull-up/pull-downs
• Output slew rate and amplitude
• Output impedance (85Ω or 100Ω) for each output
▪ Contact factory for custom default configurations
▪ 25MHz input frequency
▪ OE# pins support PCIe CLKREQ# function
▪ Pin-selectable SRnS 0%, CC 0% and CC/SRIS - 0.5% spread
▪ SMBus-selectable CC/SRIS -0.25% spread
▪ Clean switching between the CC/SRIS spread settings
▪ DIF outputs blocked until PLL is locked; clean system start-up
▪ 2 selectable SMBus addresses