• Four low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential CLK, nCLK pairs can accept the following
differential input levels: LVDS, CML
• Maximum input clock frequency: 1.5GHz
• LVCMOS/LVTTL interface levels for the control input select
• Output skew: 10ps (typical)
• Propagation delay: 400ps (maximum)
• Low propagation delay variation across temperature for 1PPS
applications
• Low additive phase jitter, RMS; fREF = 156.25MHz,
10kHz–20MHz: 34fs (typical)
• Device current consumption (IDD):
• 65mA typical: 1.8V
• 75mA typical: 2.5V
• Full 1.8V or 2.5V supply voltage
• Lead-free (RoHS 6), 16-Lead VFQFPN package
• -40°C to +85°C ambient operating temperature
• Supports case temperature up to +105°C
• Supports PCI Express Gen 1-5