Ultra-low power consumption technology
• VDD = single power supply voltage of 1.6 to 3.6 V
• HALT mode
• STOP mode
• SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed from high
speed (0.04167 μs: @ 24 MHz operation with high-speed on-chip
oscillator clock or PLL clock) to ultra-low speed (30.5 μs: @ 32.768
kHz operation with subsystem clock)
• Multiply/divide and multiply/accumulate instructions are supported.
• Address space: 1 Mbyte
• General-purpose registers: (8-bit register × 8) × 4 banks
• On-chip RAM: 8 to 16 KB
Code flash memory
• Code flash memory: 64 to 256 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security function)
• On-chip debug function
• Self-programming (with boot swap function/flash shield window function)