Ultra-Low Power Technology
• 2.4 V to 5.5 V operation from a single supply
• Stop (RAM retained): 0.23 μA, (LVD enabled): 0.31 μA
• Halt (RTC + LVD): 0.57 μA
• Supports snooze
• Operating: 71 μA/MHz
16-bit RL78 CPU Core
• Delivers 31 DMIPS at maximum operating frequency
of 24 MHz
• Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC Architecture (Harvard) with 3-stage pipeline
• Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
Code Flash Memory
• Density: 32 KB
• Block size: 1 KB
• On-chip single voltage flash memory with protection
from block erase/writing
• Self-programming with secure boot swap function
and flash shield window function
Data Flash Memory
• Data Flash with background operation
• Data flash size: 2 KB
• Erase Cycles: 1 Million (typ.)
• Erase/programming voltage: 2.4 V to 5.5 VRAM
• 5.5 KB size options
• Supports operands or instructions
• Back-up retention in all modes