1.1 Features
 Minimum instruction execution time can be changed
from high speed (0.03125 μs: @ 32 MHz operation with
high-speed on-chip oscillator clock or PLL clock) to ultra
low-speed (66.6 μs: @ 15 kHz operation with lowspeed
on-chip oscillator clock)
 General-purpose register: 8 bits × 32 registers (8 bits ×
8 registers × 4 banks)
 ROM: 128K to 512KB
 RAM: 10K to 32KB
 Data flash memory: 8KB/16KB
 High-speed on-chip oscillator clock
Selectable from 32 MHz (Typ.), 24 MHz (Typ.), 16 MHz (Typ.),
12 MHz (Typ.), 8 MHz (Typ.), 4 MHz (Typ.), and 1 MHz (Typ.)
(Selectable from 64 MHz (Typ.) and 48 MHz (Typ.) when using Timer RD)
 Low-speed on-chip oscillator clock: 15 kHz × 2
channels (one for WWDT and one for CPU and
peripherals other than WWDT)
 On-chip PLL (×3, ×4, ×6, ×8)
 On-chip single-power-supply flash memory (with
prohibition of block erase/writing function)
 Self-programming (with boot swap function/flash shield window function)
 On-chip debug function
 On-chip power-on-reset (POR) circuit and voltage detector (LVD)
 On-chip watchdog timer (operable with the dedicated
low-speed on-chip oscillator clock)
 Multiply/divide/multiply & accumulate instructions are supported
16 bits × 16 bits = 32 bits (Unsigned or signed)
32 bits ÷ 32 bits = 32 bits (Unsigned)
16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
 On-chip key interrupt function
 On-chip clock output/buzzer output controller
 On-chip BCD adjustment
 I/O ports: 44 to 136 (including one input-only pin)
 Timer
- 16-bit timer array unit: 16 to 24 channels
- 16-bit timer RD: 2 channels (six triangle-wave
outputs; sawtooth wave/triangle-wave modulation)