Description
The M54/74HC259 is a high speed CMOS 8 BIT ADDRESSABLE LATCH fabricated in silicon gate C2MOS technology. It has the same highspeed performance of LSTTL combined with true CMOS low power consumption. The M54HC259/M74HC259 has single data input (D) 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), common enable input (E), and a common CLEAR input. To operate this device as an addressable latch, data is held on the D input, and the addressof the latch into which the data isto beentered is held on the A, B, and C inputs. When ENABLE is taken low the data flows through to the addresses output. The data is stored on the positive-going edge of the ENABLE pulse. Allunaddressed latches will remain unaffected. With ENABLE in the high state the device is deselected and all latches remain in their previous state, unaffected by changes onthe data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the ENABLE should be held high (inactive) while the addresslines are changing. IfENABLE isheld highand CLEAR is taken low all eight latches are cleared to the low state. IfENABLE islowall latches except the addressed latch will be cleared. The addressed latch will instead follow the Dinput, effectively implementing a 3-to 8 line decoder. All inputs are equipped with protection circuits against static discharge and transient excess voltage. 1/12