▪ High-performance clock RF-PLL with support for JESD204B
▪ Optimized for low-phase noise: -150dBc/Hz (800kHz offset;
245.76MHz clock)
▪ Integrated phase noise of 80fs RMS typical (12kHz–20MHz)
▪ Dual-PLL architecture
▪ First PLL stage with external VCXO for clock jitter attenuation
▪ Second PLL with internal FemtoClock NG PLL:2949.12 MHz
▪ Six output channels with a total of 19 outputs, organized in:
— Four JESD204B channels (device clock and SYSREF output)
with two, four and six outputs
— One clock channel with two outputs
— One VCXO output
▪ Configurable integer clock frequency dividers
▪ Supported clock output frequencies include: 2949.12, 1474.56,
983.04, 491.52, 245.76, and 122.88MHz
▪ Low-power LVPECL/LVDS outputs support configurable signal
amplitude, DC and AC coupling and LVPECL, LVDS line
terminations techniques