Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced VOH (Typically = 3.3 V) Versions of
Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Fully Compatible With TTL Input and
Output Logic Levels
64-mA Output Sink Current
32-mA Output Source Current

description
The CY74FCT399T is a high-speed quad 2-input register that selects four bits of data from either of two sources
(ports) under control of a common select (S) input. Selected data are transferred to a 4-bit output register
synchronous with the low-to-high transition of the clock (CP) input. The 4-bit D-type output register is fully edge
triggered. The data inputs (I0X, I1X) and S input must be stable only one setup time prior to, and hold time after,
the low-to-high transition of CP for predictable operation. The CY74FCT399T has noninverted outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.