Features:
® Two independent 4-bit latches
® Individual master reset for each 4-bit latch
® 3.state outputs with high-impedance state for bus
line applications
= Medium-speed operation: tp = tp 4 = 70 ns
{typ.) at Vpp = 10 Vand C_= 50 pF
® 100% tested for quiescent current at 20 V
® 5-V, 10-V, and 16-V parametric ratings
= Standardized, symmetrical output characteristics
® Maximum input current of 1 yA at 18 V
over full package-temperature range;
100 nA at 18 V and 26°C
= Noise margin (full package-temperature
range) =
1VatVpp= 5V
2VatVpp=10V
25VatVpp=15V
® Meets all requirements of JEDEC Tenta-
tive Standard No. 13B,"Standard Speci-
fications for Description of ‘B’ Series
CMOS Devices”