Functional Description
The CY7C1333 is a 3.3V, 64K by 32 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1333 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. The CY7C1333 is pin/functionally compatible to ZBT SRAM MT55L64L32F.

Features
• Pin compatible and functionally equivalent to ZBT™ device MT55L64L32F
• Supports 66-MHz bus operations with zero wait states
    — Data is transferred on every clock
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for Flow-Through operation
• Byte Write capability
• 64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
    — 12.0 ns (for 66-MHz device)
    — 14.0 ns (for 50-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-pin TQFP package
• Burst Capability—linear or interleaved burst order
• Low (16.5 mW) standby power