FEATURES
► Flexible, reconfigurable common platform design
► 4 DAC cores connected to various DSP and bypass datapaths
► Supports single, dual, and quad band
► Datapaths and DSP blocks are fully bypassable
► On-chip PLL with multichip synchronization
► External RFCLK input option for off-chip PLL
► Maximum DAC sample rate up to 12 GSPS
► Maximum data rate up to 12 GSPS using JESD204C
► Useable analog bandwidth to 8 GHz
► DAC ac performance at 12 GSPS
► Full-scale output current range: 6.43 mA to 37.75 mA
► Two-tone IMD3 (−7 dBFS per tone): −78.9 dBc
► NSD, single-tone at 3.7 GHz: −155.1 dBc/Hz
► SFDR, single-tone at 3.7 GHz: −70 dBc
► Versatile digital features
► Selectable interpolation filters
► Configurable or bypassable DUCs
► 8 fine complex DUCs and 4 coarse complex DUCs
► 48-bit NCO per DUC
► Option to bypass fine and coarse DUC
► Programmable delay per datapath
► Transmit DPD support
► Fine DUC channel gain control and delay adjust
► Auxiliary features
► Direct digital synthesis and fast frequency hopping
► Low latency loopback mode (receive datapath NCO outputs
can be routed to the transmit datapaths)
► Power amplifier downstream protection circuitry
► On-chip temperature monitoring unit
► Flexible GPIO pins
► TDD power savings option
► SERDES JESD204B/JESD204C interface
► 8-lane JESD204B/C receiver (JRx)
► JESD204B compliance with the maximum 15.5 Gbps
► JESD204C compliance with the maximum 24.75 Gbps
► Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
► 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch
APPLICATIONS
► Wireless communications infrastructure
► Microwave point to point, E-band and 5G mmWave
► Broadband communications systems
► DOCSIS 3.1 and 4.0 CMTS
► Phased array radar and electronic warfare
► Electronic test and measurement systems