56F801 General Description

• Up to 30 MIPS operation at 60MHz core frequency

• Up to 40 MIPS operation at 80MHz core frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14

addressing modes

• Hardware DO and REP loops

• 6-channel PWM Module

• Two 4-channel, 12-bit ADCs

• Serial Communications Interface (SCI)

• Serial Peripheral Interface (SPI)

•8K ×16-bit words (16KB) Program Flas

•1K ×16-bit words (2KB) Program RAM

•2K ×16-bit words (4KB) Data Flash

•1K ×16-bit words (2KB) Data RAM

•2K ×16-bit words (4KB) Boot Flash

• General Purpose Quad Timer

• JTAG/OnCE^TM port for debugging

• On-chip relaxation oscillator

• 11 shared GPIO

• 48-pin LQFP Package

56F801 Features

Digital SignalProcessing Core

• Efficient 16-bit 56800 family controller engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

• Single-cycle 16 ×16-bit parallel Multiplier-Accumulator (MAC)

• Two 36-bit accumulators including extension bits

• 16-bit bidirectional barrel shifter

• Parallel instruction set with unique processor addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE debug programming interface



Memory

• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

• On-chip memory including a low-cost, high-volume Flash solution

—8K ×16 bit words of Program Flash

—1K ×16-bit words of Program RAM

—2K ×16-bit words of Data Flash

—1K ×16-bit words of Data RAM

—2K ×16-bit words of Boot Flash

• Programmable Boot Flash supports customized boot code and field upgrades of stored code through a variety of interfaces (JTAG, SPI)



Peripheral Circuits for 56F801

• Pulse Width Modulator (PWM) with six PWM outputs, two Fault inputs, fault-tolerant design with deadtime

insertion; supports both center- and edge-aligned modes

• Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with two

4-multiplexed inputs; ADC and PWM modules can be synchronized

• General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines)

• Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)

• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)