Introduction

The MC9S12C-Family / MC9S12GC-Family are 48/52/80 pin Flash-based MCU families, which deliver the power and flexibility of the 16-bit core to a whole new range of cost and space sensitive, general purpose industrial and automotive network applications. All MC9S12C-Family / MC9S12GC-Family members feature standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit pulse width modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC).

Features

• 16-bit HCS12 core:

   — HCS12 CPU

   – Upward compatible with M68HC11 instruction set

   – Interrupt stacking and programmer’s model identical to M68HC11

   – Instruction queue

   – Enhanced indexed addressing

   — MMC (memory map and interface)

   — INT (interrupt control)

   — BDM (background debug mode)

   — DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer)

   — MEBI (multiplexed expansion bus interface) available only in 80-pin package version

• Wake-up interrupt inputs:

   — Up to 12 port bits available for wake up interrupt function with digital filtering

• Operating frequency:

   — 32MHz equivalent to 16MHz bus speed for single chip

   — 32MHz equivalent to 16MHz bus speed in expanded bus modes

   — Option of 9S12C Family: 50MHz equivalent to 25MHz bus speed

   — All 9S12GC Family members allow a 50MHz operating frequency.

• Internal 2.5V regulator:

   — Supports an input voltage range from 2.97V to 5.5V

   — Low power mode capability

   — Includes low voltage reset (LVR) circuitry

   — Includes low voltage interrupt (LVI) circuitry

• 48-pin LQFP, 52-pin LQFP, or 80-pin QFP package:

   — Up to 58 I/O lines with 5V input and drive capability (80-pin package)

   — Up to 2 dedicated 5V input only lines (IRQ, XIRQ)

   — 5V 8 A/D converter inputs and 5V I/O

• Development support:

   — Single-wire background debug™ mode (BDM)

   — On-chip hardware breakpoints

   — Enhanced DBG12 debug features