1 General description
The 74ALVCH162827 20-bit buffers provide high performance bus interface buffering
for wide data/address paths or buses carrying parity. They have NAND output enables
(nOE1 and nOE2) for maximum control flexibility.
The 74ALVCH162827 is designed with 30 Ω series resisters in both the pull-up and pulldown
output structures. This design reduces line noise in applications such as memory
address drivers, clock drivers and bus receivers/transmitters.
To ensure the high impedance state during power up or power down, nOEn should be
tied to VCC through a pullup resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
The 74ALVCH162827 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2 Features and benefits
• CMOS low power consumption
• MultiByte flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Direct interface with TTL levels (2.7 V to 3.6 V)
• Bus hold on data inputs
• Current drive ± 12 mA at 3.0 V
• Integrated 30 Ω termination resistors
• Complies with JEDEC standards:
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
– CDM JESD22-C101E exceeds 1000 V