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8P79818 Datasheet (PDF) - Renesas Technology Corp

8P79818 Datasheet PDF - Renesas Technology Corp
No. de pieza 8P79818
Descarga  8P79818 Descarga
Tamaño del archivo   1180.54 Kbytes
Page   34 Pages
Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp
Descripción Electrónicos Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

8P79818 Datasheet (PDF)

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8P79818 Datasheet PDF - Renesas Technology Corp

No. de pieza 8P79818
Descarga  8P79818 Click to download

Tamaño del archivo   1180.54 Kbytes
Page   34 Pages
Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp
Descripción Electrónicos Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

8P79818 Datasheet (HTML) - Renesas Technology Corp


8P79818 Detalles de producto

Description
The device is intended to take 1 or 2 reference clocks, select
between them, using a pin or register selection and generate up to 8
outputs that may be the same as the reference frequency or
integer-divider versions of it.
The 8P79818 supports two output banks, each with its own divider
and power supply. All outputs in one bank would generate the same
output frequency, but each output can be individually controlled for
output type, output enable or even powered-off.
The device supports a serial port for configuration of the parameters
while in operation. The serial port can be selected to use the I
2
C or
SPI protocol. After power-up, all outputs will come up in LVDS mode
and may be programmed to other configurations over the serial port.
Outputs may be enabled or disabled under control of the OE input
pin.
The device can operate over the -40°C to +85°C temperature range.

Features
▪ Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS
reference clocks
— Accepts input frequencies ranging from 1PPS (1Hz) to
700MHz
▪ Select which of the two input clocks is to be used as the reference
clock for which divider via pin or register selection
— Switchover will not generate any runt clock pulses on the
output
▪ Generates eight differential outputs
or eight LVCMOS outputs, Bank A only
— Differential outputs selectable as LVPECL, LVDS, CML or
HCSL
— Differential outputs support frequencies from 1PPS to 700MHz
— LVCMOS outputs support frequencies from 1PPS to 200MHz
— LVCMOS outputs in the same pair may be inverted or in-phase
relative to one another
▪ Outputs arranged in 2 banks of 4 outputs each
— Each bank supports a separate power supply of 3.3V, 2.5V or
1.8V
— 1.5V output voltage is also supported for LVCMOS, Bank A
only
— One divider per output bank, supporting divide ratios of 2...511
or divider bypass
▪ Output enable control pin
— Output enable or disable will not cause any runt pulses
▪ Register programmable via I
2
C / SPI serial port
— Individual output enables, output type selection and output
power-down control bits supported
— Input mux selection control bit
▪ Core voltage supply of 3.3V, 2.5V or 1.8V
▪ -40°C to +85°C ambient operating temperature
▪ Lead-free (RoHS 6) packaging




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Acerca de Renesas Technology Corp


Renesas Technology Corp es una compañía de semiconductores japoneses que proporciona una amplia gama de microcontroladores, sistemas a chips y dispositivos analógicos y de energía para diversas aplicaciones en los mercados automotrices, industriales y de consumo.
La compañía se formó en 2010 a través de la fusión de NEC Electronics Corporation y Renesas Technology Corporation.
Renesas es uno de los mayores proveedores de microcontroladores del mundo y es conocido por su experiencia en el desarrollo de tecnologías avanzadas en áreas como Internet de las cosas (IoT), inteligencia artificial (IA) y electrónica automotriz.
La compañía tiene operaciones en más de 20 países y sus productos se utilizan en una amplia gama de aplicaciones.

*Esta información es solo para fines informativos generales, no seremos responsables de ninguna pérdida o daño causado por la información anterior.




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