The 8V19N882 is a fully integrated FemtoClock® RF
Sampling Clock Generator and Jitter Attenuator. The
device is designed as a high-performance clock
solution for conditioning and frequency/phase
management of wireless base station radio
equipment boards. The 8V19N882 is optimized to
deliver excellent phase noise performance as
required in 4G, 5G, and including mmWave radio
implementations. The device supports JESD204B
(subclass 0 and 1) and JESD204C.
A two-stage PLL architecture supports both jitter
attenuation and frequency multiplication. The first
stage PLL is the jitter attenuator and uses an external
VCXO for best possible phase noise characteristics.
The second stage PLL locks on the first PLL output
signal and synthesizes the target frequency. The
second stage PLL can use the internal or an external
high-frequency VCO.
The 8V19N882 generates the high-frequency clocks
and the low-frequency synchronization signals
(SYSREF) from the selected VCO. SYSREF signals
are internally synchronized to the clock signals. The
integrated signal delay blocks can be used to achieve
phase alignment, controlled phase offsets between
system reference and clock signals, and to
align/delay individual output signals. The two
redundant inputs are monitored for activity. Four
selectable clock switching modes can handle clock
input failure scenarios. Auto-lock, individually
programmable output frequency dividers, and phase
adjustment capabilities are added for flexibility.
The 8V19N882 is configured through a 3/4-wire SPI
interface and reports lock and signal loss status in
internal registers and via the GPIO[1:0] outputs.
Internal status bit changes can also be reported via a
GPIO output.

Features
▪ High-performance clock RF sampling clock
generator and clock jitter attenuator with support
for JESD204B/C
▪ Low phase noise: -144.7dBc/Hz (800kHz offset;
491.52MHz)
▪ Integrated phase noise of 74fs RMS (12k-20MHz,
491.52MHz)
▪ Dual-PLL architecture with internal and optional
external VCO
▪ Eight output channels with a total of 16 outputs
▪ Configurable integer clock frequency dividers
▪ Clock output frequencies: up to 3932.16MHz
(Internal VCO) and  6GHz (optional external VCO)
▪ Differential, low noise I/O
▪ Deterministic phase delay and integrated phase
delay circuits
▪ Redundant input clock architecture with two inputs
and monitors, holdover, and input switching
▪ SPI 3/4 wire configuration interface
▪ Supply voltage: 1.8V, 2.5V, and 3.3V
▪ Package: 76 VFQFN (9 x 9 mm²)
▪ Temperature range: -40°C to +105°C (board)

Applications
▪ Wireless infrastructure applications: 4G, 5G, and
mmWave
▪ Data acquisition: jitter-sensitive ADC and DAC
circuits
▪ Radar, imaging, instrumentation, and medical