General Description
The PL133-67 is an advanced fanout buffer design for
high performance, low-power, small form factor
applications. The PL133-67 accepts a reference clock
input from DC to 150 MHz and provides six outputs of
the same frequency.
The PL133-67 is offered in a TSSOP-16L package and
it offers the best phase noise, additive jitter
performance, and lowest power consumption of any
comparable IC.
The PL133-67 outputs can be disabled to a high
impedance (tri-state) by pulling low the OE pin. When
the OE pin is high, the outputs are enabled and follow
the REF input signal. When the OE pin is left open, a
pull-up resistor on the chip will default the OE pin to
logic 1 so the outputs are enabled.

Features
• 1:6 LVCMOS Output Fanout Buffer from DC
to150 MHz
• Low Additive Phase Jitter of 60 fs RMS
• 8 mA Output Drive Strength
• Low Power Consumption for Portable
Applications
• Low Input-Output Delay
• Output-Output Skew <250 ps
• 2.5V to 3.3V, ±10% Operation
• 1.8V +10%/–5% Operation up to 67 MHz
• Operating Temperature Range:
- Commercial: 0°C to +70°C
- Industrial: –40°C to +85°C
• Available in 16-Pin TSSOP Package