OVERVIEW
The EP7211 is designed for ultra-low-power applications such as organizers/PDAs, two-way pagers, smart cellular phones, and industrial hand-held information appliances. The core-logic functionality of the device is built around an ARM720T processor with 8 kbytes of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU), which allows for Microsoft Windows CE support.

FEATURES
■ Dynamically programmable clock speeds of 18, 36, 49, and 74 MHz at 2.5 V
■ Performance matching 100-MHz Intel Pentium-based PC
■ Socket and register compatible with CL-PS7111
■ Ultra low power
    — Designed for applications that require long battery life while using standard AA/AAA batteries or rechargeable cells
    — 170 mW at 74 MHz in the Operating State
    — 50 mW at 18 MHz in the Operating State
    — 15 mW in the Idle State (clock to the CPU stopped, everything else running)
    — 10 µW in the Standby State (realtime clock ‘on’, everything else stopped)
■ LCD controller
    — Interfaces directly to a single-scan panel monochrome LCD
    — Panel width size is programmable from 32 to 1024 pixels in 16-pixel increments
    — Video frame buffer size programmable up to 128 kbytes
    — Bits per pixel programmable from 1, 2, or 4
■ ARM720T processor
    — ARM7TDMI CPU
    — 8 kbytes of four-way set-associative cache
    — MMU with 64-entry TLB (transition look aside buffer)
    — Write buffer
    — Windows CE enabled
    — Thumb® code support enabled
■ DRAM controller
    — Supports both 16- and 32-bit-wide DRAMs
    — EDO support (fast page mode support for 13 MHz and 18 MHz operation only)
■ ROM/SRAM/FLASH memory control
    — Decodes 4, 5, or 6 separate memory segments of up to 256 Mbytes each
    — Each segment can be configured as 8, 16, or 32 bits wide and supports page-mode access
    — Programmable access time for conventional ROM/SRAM/Flash memory
■ 37.5 kbytes of on-chip SRAM for fast program execution and/or as a frame buffer
■ On-chip ROM; for manufacturing boot-up support
■ Four synchronous serial interfaces
    — ADC (SSI1) Interface: Master mode only; SPI1 and Microwire12-compatible (128 kbps operation)
    — SSI2 Interface: Master/Slave mode; SPI/Microwire2 compatible (512 kbps operation)
    — Audio Codec Interface (64 kbps operation)
    — Multimedia Codec Port (Interfaces to Philips’ UCB1100 and UCB1200 codecs) (9.216 Mbps operation)
■ 27 bits of general-purpose I/O
    — Three 8-bit and one 3-bit GPIO port
    — Supports scanning keyboard matrix
■ Two UARTs (16550 type)
    — Supports bit rates up to 115.2 kbps
    — Contains two 16-byte FIFOs for TX and RX
    — UART1 supports modem control signals
■ SIR (up to 115.2 kbps) infrared encoder
    — IrDA (Infrared Data Association) SIR protocol encoder can be optionally switched into TX and RX signals of UART1
■ PWM interface
    — Provides two 96-kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a DC-to-DC converter
■ Two timer counters
■ 208-pin LQFP or 256-ball PBGA packages
■ Evaluation kit available with BOM, schematics, sample code, and design database
■ Support for up to two ultra-low-power CL-PS6700 PC Card controllers
■ Dedicated LED flasher pin from RTC
■ Full JTAG boundary scan and Embedded ICE support