| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
ST72F324J Datasheet(PDF) 141 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST72F324J Datasheet(HTML) 141 Page - STMicroelectronics |
|
141 / 156 page ![]() ST72324J/K 141/156 12.12 10-BIT ADC CHARACTERISTICS Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Figure 93. RAIN max. vs fADC with CAIN=0pF 4) Figure 94. Recommended CAIN & RAIN values. 5) Figure 95. Typical A/D Converter Application Notes: 1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide- lines and are not tested. 2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS. 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k Ω). Data based on characterization results, not tested in production. 4. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca- pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 5. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization and to allow the use of a larger serial resistor (RAIN). Symbol Parameter Conditions Min Typ 1) Max Unit fADC ADC clock frequency 0.4 2 MHz VAREF Analog reference voltage 2) 0.7*VDD 5.5 V VAIN Conversion voltage range 3) VSSA VAREF IL Input leakage current for analog input -40°C ≤T A≤85°C range ±250 nA Other TA ranges ±1 µA RAIN External input impedance see Figure 93 and Figure 943)4)5) k Ω CAIN External capacitor on analog input pF fAIN Variation freq. of analog input signal Hz CADC Internal sample and hold capacitor 12 pF tSTAB Stabilization time after ADC enable fCPU=8MHz, SPEED=0 fADC=2MHz 0 5) µs tADC Conversion time (Sample+Hold) 7.5 - No of sample capacitor loading cycles - No. of Hold conversion cycles 4 11 1/fADC 0 5 10 15 20 25 30 35 40 45 010 30 70 CPARASITIC (pF) 2 MHz 1 MHz 0.1 1 10 100 1000 0.01 0.1 1 10 fAIN(KHz) Cain 10 nF Cain 22 nF Cain 47 nF AINx ST72XXX VDD IL ±1 µA VT 0.6V VT 0.6V CADC 6pF VAIN RAIN 10-Bit A/D Conversion 2k Ω(max) CAIN |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |