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ST72F324J Datasheet(PDF) 133 Page - STMicroelectronics

No. de pieza ST72F324J
Descripción Electrónicos  8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
PDF  156 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72F324J Datasheet(HTML) 133 Page - STMicroelectronics

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EMC CHARACTERISTICS (Cont’d)
True Open Drain Pin Protection
The centralized protection (4) is not involved in the
discharge of the ESD stresses applied to true
open drain pads due to the fact that a P-Buffer and
diode to VDD are not implemented. An additional
local protection between the pad and VSS (5a &
5b) is implemented to completely absorb the posi-
tive ESD discharge.
Multisupply Configuration
When several types of ground (VSS, VSSA, ...) and
power supply (VDD, VAREF, ...) are available for
any reason (better noise immunity...), the structure
shown in Figure 79 is implemented to protect the
device against ESD.
Figure 77. Positive Stress on a True Open Drain Pad vs. VSS
Figure 78. Negative Stress on a True Open Drain Pad vs. VDD
Figure 79. Multisupply Configuration
IN
VDD
VSS
(1)
(2b)
(4)
OUT
VDD
VSS
(3b)
Main path
Path to avoid
(5a)
(5b)
IN
VDD
VSS
(1)
(2b)
(4)
OUT
VDD
VSS
(3b)
Main path
(3b)
(3b)
VAREF
VSSA
VAREF
VDD
VSS
BACK TO BACK DIODE
BETWEEN GROUNDS
VSSA



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