LED171596ARSLR datasheet(147/153 Pages) TI1

147 / 153 page

147

LED171596A

www.ti.com

SNVSAY2 – OCTOBER 2017

Submit Documentation Feedback

Figure 309. LED PWM Phase Shift 3

9 Power Supply Recommendations

9.1 Power Start-up and Shutdown Sequence

The preferred power start-up sequence for the LED171596A is to apply VDD first then VDDIO followed by VLED

while keeping EN input low where t1

≥ t2 ≥ 0 (refer to ). The VDD and VDDIO supplies can be applied

simultaneously provided that VDD

≥ VDDIO in transition. The preferred power shutdown sequence is the exact

opposite of start-up, EN set low then VLED removed followed by VDDIO removed and finally VDD removed

where t1

≥ t2 ≥ t3 ≥ 0 (refer to ).

9.2 VLED Input Supply Recommendations

The LED171596A is designed to operate from a 0-V to 6.1-V VLED voltage supply. The VLED supply must be

well regulated and able to provide the peak current required by the LED configuration without voltage drop under

load transients (start-up or rapid brightness change). The resistance of the input supply rail must be low enough

such that the input current transient does not cause the VLED supply voltage to droop below LED Vf + VSAT

voltage. TI recommends bulk decoupling located close to the VLED pin to minimize the impact of the VLED input

supply rail resistance.

9.3 VDD Input Supply Recommendations

The LED171596A is designed to operate from a 2.9-V to 3.5-V VDD voltage supply. This input supply must be

well regulated and be able to provide the peak current required by the LED configuration. The resistance of the

VDD supply rail must be low enough such that the input current transient does not cause the LED171596A VIN

supply voltage to droop below the maximum VDDPOR voltage. Additional bulk decoupling located close to the

VDD bypass capacitor may be required to minimize the impact of the VDD input supply rail resistance.

LED171596ARSLR Datasheet(PDF) 147 Page - Texas Instruments