MPXM2102AS datasheet(465/670 Pages) MOTOROLA

465 / 670 page

AN1525

3–319

Motorola Sensor Device Data

www.motorola.com/semiconductors

Figure 1. Positioning the Sensor’s Full–Scale Span within the A/D’s or Amplifier’s Dynamic Range

A/D HIGH REFERENCE OR HIGH

SATURATION LEVEL OF AMPLIFIER

FULL–SCALE

OUTPUT VOLTAGE

A/D LOW REFERENCE OR LOW

SATURATION LEVEL OF AMPLIFIER

ZERO PRESSURE

OFFSET VOLTAGE

A similar requirement that warrants the use of a dc level

shift is the prevention of the pressure sensor’s voltage from

extending into the saturation regions of the operational

amplifiers. This also would cause a nonlinearity in the sensor

output measurements. For example, if an op–amp powered

with a single–ended 5 V supply saturates near the low rail of

the supply at 0.2 V, a positive dc level shift may be required

to position the zero pressure offset voltage at or above 0.2 V.

Likewise, if the same op–amp saturates near the high rail of

the supply at 4.8 V, a negative dc level shift may be required

to position the full–scale pressure voltage at or below 4.8 V.

It should be obvious that if the gain of the amplifiers is too

large, the span may be too large to be positioned within the

4.6 V window (regardless of ability to level shift dc offset). In

such a case, the gain must be decreased to reduce the span.

THE TWO OP–AMP GAIN STAGE

TRANSFER FUNCTION

The transfer function of the two op–amp signal–conditioning

stage, shown in Figure 2, can be determined using nodal

analysis at nodes 1 and 2. The analysis can be simplified by

calculating the transfer function for each of the signals with the

other two signals grounded (set to zero), and then employing

superposition to realize the overall transfer function. As shown

in Figure 2, VIN2 and VIN1 are the differential amplifier input

signals (with VIN2 > VIN1), and VREF is the positive dc level

adjust point. For a sensor with a small zero pressure offset

and operational amplifiers powered from a single–ended

supply, it may be necessary to add a positive dc level shift to

keep the operational amplifiers from saturating near zero

volts.

Figure 2. The Two Operational–Amplifier Gain Stage

VIN2

VIN1

VREF

NODE 1

VCC

NODE 2

VO′

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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