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RC224ATL Datasheet(PDF) 43 Page - Synaptics Incorporated. |
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RC224ATL Datasheet(HTML) 43 Page - Synaptics Incorporated. |
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43 / 104 page  RC224ATL/224ATLV 3.0 Pin Descriptions EmbeddedModem Family D224ATLVDSC Conexant 3-17 DCDL DO DCD Indicator. The DCDL output is controlled by the AT&C command. DTRL DO DTR Indicator. The DTRL output is controlled by the AT&D command. Parallel Host Interface (Parallel Interface Only) When the HWT input signal is connected to the host bus write line, the parallel interface is selected upon reset. (See Section 7.3, Interface Timing and Waveforms for waveform and timing information.) The parallel interface emulates a 16C450 UART; (See Table 2-1, Parallel Interface Registers). Parallel interface operation is equivalent to 16C450 operation with CS0 and CS1 inputs high and DISTR, DOSTR, and ADS inputs low. The corresponding RC224ATLV and 16C450 signals are shown below. 16C450 signals that are not required for RC224ATLV host computer operation are not shown. 16C450 Signal RC224ATLV Signal A0 - A2 HA0 - HA2 D0 - D7 HD0 - HD7 MR RESET (Active low) CS2 HCS DISTR HWT DOSTR HRD INTRPT HINT DDIS HDIS OUT2 None (Implemented internally in RC224ATLV) HA0-HA2 HD0-HD7 DI DIO Host Bus Address Lines 0-2. During a host read or write operation, signals HA0–HA2 select an internal register. The state of the divisor latch access bit (DLAB) affects the selection of certain registers. Host Bus Data Lines 0-7. HD0-HD7 are comprised of eight tri-state I/O lines providing bidirectional communication between the host and the modem. Data, control words, and status information are transferred through HD0-HD7. HCS DI Host Bus Chip Select. HCS input low enables reading from or writing to the modem using the parallel bus. HRD DI Host Bus Read. HRD is an active low read control input. When the modem is selected with HCS, HRD low allows status or data words to be read from an addressed register. HWT DI Host Bus Write. HWT is an active low write control input. When the modem is selected with HCS, HWT low allows data or control words to be written to an addressed register. Table 3-5. Hardware Interface Signal Definitions (3 of 5) Label I/O Type Signal Name/Description DLAB HA2 HA1 HA0 Register 0 0 0 0 Receive Buffer Register (Read), Transmitter Holding Register (Write) 0 0 0 1 Interrupt Enable Register X 0 1 0 Interrupt Identification Register (Read Only) X 0 1 1 Line Control Register X 1 0 0 Modem Control Register X 1 0 1 Line Status Register (Read Only) X 1 1 1 Scratch Register 1 0 0 0 Divisor Latch Register (Least Significant Byte) 1 0 0 1 Divisor Latch Register (Most Significant Byte) |
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Descripción similar - RC224ATL |
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