STM32F769AI datasheet(213/255 Pages) STMICROELECTRONICS

213 / 255 page

DocID029041 Rev 4

213/255

STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

Electrical characteristics

224

Table 114. SDRAM read timings(1)

1. Guaranteed by characterization results.

Symbol

Parameter

Min

Max

Unit

tw(SDCLK)

FMC_SDCLK period

2THCLK 0.5

2THCLK + 0.5

tsu(SDCLKH _Data)

Data input setup time

1.5

th(SDCLKH_Data)

Data input hold time

1.5

td(SDCLKL_Add)

Address valid time

3.5

td(SDCLKL- SDNE)

Chip select valid time

1.5

th(SDCLKL_SDNE)

Chip select hold time

0.5

td(SDCLKL_SDNRAS)

SDNRAS valid time

th(SDCLKL_SDNRAS)

SDNRAS hold time

0.5

td(SDCLKL_SDNCAS)

SDNCAS valid time

0.5

th(SDCLKL_SDNCAS)

SDNCAS hold time

Table 115. LPSDR SDRAM read timings(1)

1. Guaranteed by characterization results.

Symbol

Parameter

Min

Max

Unit

tW(SDCLK)

FMC_SDCLK period

2THCLK 0.5

2THCLK + 0.5

tsu(SDCLKH_Data)

Data input setup time

th(SDCLKH_Data)

Data input hold time

4.5

td(SDCLKL_Add)

Address valid time

2.5

td(SDCLKL_SDNE)

Chip select valid time

2.5

th(SDCLKL_SDNE)

Chip select hold time

td(SDCLKL_SDNRAS

SDNRAS valid time

0.5

th(SDCLKL_SDNRAS)

SDNRAS hold time

td(SDCLKL_SDNCAS)

SDNCAS valid time

1.5

th(SDCLKL_SDNCAS)

SDNCAS hold time

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