STM32F410RB datasheet(105/142 Pages) STMICROELECTRONICS

No. de pieza	STM32F410RB

Descripción Electrónicos	Clock, reset and supply management

PDF	142 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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DocID028094 Rev 5

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STM32F410x8/B

Electrical characteristics

118

Figure 32. SPI timing diagram - slave mode and CPHA = 0

ta(SO)

Data output access time Slave mode

tdis(SO)

Data output disable time Slave mode

tv(SO)

Data output valid time

Slave mode (after enable edge),

2.7 V < VDD < 3.6 V

-11

Slave mode (after enable edge),

1.7 V < VDD < 3.6 V

18.5

th(SO)

Data output hold time

Slave mode (after enable edge),

1.7 V < VDD < 3.6 V

tv(MO)

Data output valid time

Master mode (after enable edge)

th(MO)

Data output hold time

Master mode (after enable edge)

1. Guaranteed by characterization.

2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or

high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

having tsu(MI) = 0 while Duty(SCK) = 50%

Table 64. SPI dynamic characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

STM32F410RB Datasheet(PDF) 105 Page - STMicroelectronics