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ST72561AR7-Auto Datasheet(PDF) 309 Page - STMicroelectronics |
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ST72561AR7-Auto Datasheet(HTML) 309 Page - STMicroelectronics |
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309 / 324 page ![]() ST72561-Auto Device configuration and ordering information Doc ID 12370 Rev 8 309/324 OPT1 = reserved OPT0 = RSTC RESET clock cycle selection This option bit selects the number of CPU cycles inserted during the RESET phase and when exiting HALT mode. For resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time. 0: reset phase with 4096 CPU cycles 1: reset phase with 256 CPU cycles MS 4~8 MHz 1 0 HS 8~16 MHz 1 Table 128. OSCRANGE selection (continued) Typical frequency range OSCRANGE 10 |
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