ST72344K2 datasheet(181/247 Pages) STMICROELECTRONICS

181 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

181/247

Bit 4 = WF2 Write operation to Slave 2

This bit is set by hardware on reception of the direction bit in the I2C address byte for

Slave 2. This bit is cleared when the status register is read and there is no

communication ongoing, or when the peripheral is disabled (PE = 0)

0: No write operation to Slave 2

1: Write operation performed to Slave 2

Bit 3 = WF1 Write operation to Slave 1

This bit is set by hardware on reception of the direction bit in the I2C address byte for

Slave 1. This bit is cleared by software when the status register is read and there is no

communication ongoing, or by hardware when the peripheral is disabled (PE = 0).

0: No write operation to Slave 1

1: Write operation performed to Slave 1

Bit 2 = RF3 Read operation from Slave 3

This bit is set by hardware on reception of the direction bit in the I2C address byte for

Slave 3. It is cleared by software reading the SR register when there is no

communication ongoing. It is also cleared by hardware when the interface is disabled

(PE=0).

0: No read operation from Slave 3

1: Read operation performed from Slave 3

Bit 1= RF2 Read operation from Slave 2

This bit is set by hardware on reception of the direction bit in the I2C address byte for

Slave 2. It is cleared by software reading the SR register when there is no

communication ongoing. It is also cleared by hardware when the interface is disabled

(PE=0).

0: No read operation from Slave 2

1: Read operation performed from Slave 2

Bit 0= RF1 Read operation from Slave 1

This bit is set by hardware on reception of the direction bit in the I2C address byte for

Slave 1. It is cleared by software reading SR register when there is no communication

ongoing. It is also cleared by hardware when the interface is disabled (PE=0).

0: No read operation from Slave 1

1: Read operation performed from Slave 1

I2C byte count register (I2C3SBCR)

Reset value: 0000 0000 (00h)

Bits 7:0 = NB [7:0] Byte Count Register

This register keeps a count of the number of bytes received or transmitted through any

of the three addresses. This byte count is reset after reception by a slave address of a

new transfer and is incremented after each byte is transferred. This register is not

limited by the full page length. It is also cleared by hardware when the interface is

disabled (PE =0).

NB7

NB6

NB5

NB4

NB3

NB2

NB1

NB0

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ST72344K2 Datasheet(PDF) 181 Page - STMicroelectronics

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