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PC87309VLJ Datasheet(PDF) 183 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de pieza PC87309VLJ
Descripción Electrónicos  PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging
PDF  192 Pages
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Fabricante Electrónico  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87309VLJ Datasheet(HTML) 183 Page - National Semiconductor (TI)

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Device Specifications
183
www.national.com
10.3.13 Reset Timing
Note:
In PC-AT mode, the DRQ and IRQ signals of the FDC are in TRI-STATE after time tSRC.
1. The software reset pulse width is 100 nsec.
2. Not tested. Guaranteed by design.
10.3.14 FDC - Write Data Timing
tDRP tICP tWDW Values
1. Not tested. Guaranteed by design.
1. tCP is the Clock Period defined in Section 10.3.2 "Clock Timing" on page 171.
Symbol
Parameter
Min
Max
Unit
tRW
Reset Width1
100
µsec
tSRC
Reset to Control Inactive2
300
nsec
tRW
tSRC
MR
DRQ,
INT,
WGATE (Note)
Symbol
Parameter
Min
Max
Unit
tHDH
HDSEL Hold from WGATE Inactive1
750
µsec
tHDS
HDSEL Setup to WGATE Active1
100
µsec
tWDW
Write Data Pulse Width
See tDRP tICP
tWDW Values below
Data Rate
tDRP
tICP
tICP Nominal
tWDW
tWDW Minimum
Unit
1 Mbps
1000
6 x tCP
1
125
2 x tICP
250
nsec
500 Kbps
2000
6 x tCP
1
125
2 x tICP
250
nsec
300 Kbps
3333
10 x tCP
1
208
2 x tICP
375
nsec
250 Kbps
4000
12 x tCP
1
250
2 x tICP
500
nsec
tHDS
tHDH
tWDW
HDSEL
WGATE
WDATA



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