LAN89730 datasheet(153/218 Pages) MICROCHIP

No. de pieza	LAN89730

Descripción Electrónicos	Implements Reduced Power Operating Modes

PDF	218 Pages

Scroll/Zoom	100%

Fabricante Electrónico	MICROCHIP [Microchip Technology]

Página de inicio	http://www.microchip.com

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 2013-2015 Microchip Technology Inc.

DS60001348A-page 153

LAN89730

6.3.25

TRANSMIT FIFO LEVEL DEBUG REGISTER (DBG_TX_FIFO_LVL)

Address:

078h

Size:

32 bits

Bits

Description

Type

Default

31:28

RESERVED

27:16

TX FIFO Read Level (TXRDLVL)

This is a DWORD count defined as follows:

The count is increased by the number of DWORDs contained in the packet

after the ENTIRE packet has been written into the FIFO.

As a packet is read from the FIFO, it is decremented each time a DWORD is

read.

Note:

Rewinds are not supported.

000h

15:12

RESERVED

11:0

TX FIFO Write Level (TXWRLVL)

This is a DWORD count defined as follows:

As a packet is written into the FIFO, it is incremented each time a DWORD is

written.

Whenever a COMPLETE packet has been read from the FIFO, it is decreased

by the number of DWORDs contained in the packet.

On rewind, it is decreased by the number of DWORDs of the packet that has

currently been transferred into the FIFO.

Note:

Write side rewinds are supported, i.e., if a USB packet is received

with an error, the packet is rewound out and re-received from the

host.

000h

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