MC14020B_14 datasheet(1/7 Pages) ONSEMI

No. de pieza	MC14020B

Descripción Electrónicos	14-Bit Binary Counter

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August, 2014 − Rev. 9

1

Publication Order Number:

MC14020B/D

MC14020B

14-Bit Binary Counter

The MC14020B 14−stage binary counter is constructed with MOS

P−Channel and N−Channel enhancement mode devices in a single

monolithic structure. This part is designed with an input wave shaping

circuit and 14 stages of ripple−carry binary counter. The device

advances the count on the negative−going edge of the clock pulse.

Applications include time delay circuits, counter controls, and

frequency−dividing circuits.

Features

• Fully Static Operation

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range

• Buffered Outputs Available from stages 1 and 4 thru 14

• Common Reset Line

• Pin−for−Pin Replacement for CD4020B

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage Range

−0.5 to +18.0

V

Vin, Vout

Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD + 0.5

V

Iin, Iout

Input or Output Current

(DC or Transient) per Pin

±10

mA

PD

Power Dissipation, per Package

(Note 1)

500

mW

TA

Ambient Temperature Range

−55 to +125

°C

Tstg

Storage Temperature Range

−65 to +150

°C

TL

Lead Temperature

(8−Second Soldering)

260

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

1. Temperature Derating: “D/DW” Packages: –7.0 mW/

_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

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MARKING DIAGRAMS

SOIC−16

TSSOP−16

14020BG

AWLYWW

A

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W

= Work Week

G or

G

= Pb−Free Indicator

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

1

16

14

020B

ALYW

G

1

16

(Note: Microdot may be in either location)

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

PIN ASSIGNMENT

13

14

15

16

9

10

11

12

5

4

3

2

1

8

7

6

Q9

Q8

Q10

Q11

VDD

Q1

C

R

Q6

Q14

Q13

Q12

VSS

Q4

Q7

Q5

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