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CS89712 Datasheet(PDF) 156 Page - Cirrus Logic

No. de pieza CS89712
Descripción Electrónicos  HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER
PDF  170 Pages
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Fabricante Electrónico  CIRRUS [Cirrus Logic]
Página de inicio  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS89712 Datasheet(HTML) 156 Page - Cirrus Logic

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CS89712
156
DS502PP2
NOP
T1
T2
T3
T4
T6
T7
T8
T9
T10
CLK
nRAS /
nCAS / nWE
T0
NOP
NOP
NOP
(ACT)
CKE
nCS
1 dev
1 dev
DQM
DQ
DI0
DI1
DI2
DI3
Bank sel
A10
(prech sel)
addr
CAS lat 3
tRCD
tRP
tRAS
tRC
auto precharge
row
col
row
bank
bank
T5
NOP
T11
ACT
NOP
READ
NOP
NOP
NOP
NOP
Figure 28. SDRAM Read Cycles CAS Latency = 3
Note:
tRC1 (REF to REF/ACT command period [refresh]) = 90 ns or 4 cycles at 36 MHz.
T1
T2
T3
T4
T5
T6
T7
CLK
nRAS /
nCAS / nWE
NOP
ACT
NOP
T0
WRITE NOP
NOP
NOP
NOP
NOP
CKE
nCS
1 dev
1 dev
DQM
DQ
Bank sel
A10
(prech sel)
addr
tRCD
tRP
tRAS
tRC
tDPL
DO0
DO1
DO2
DO3
(ACT)
row
col
row
bank
bank
auto precharge
Figure 29. SDRAM Write Cycles
Note:
tDPL (data in to PRE command period command) = 10 ns or 1 cycle at 36 MHz.



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