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TMS320DM355CZCEA13 Datasheet(PDF) 126 Page - Texas Instruments

No. de pieza TMS320DM355CZCEA13
Descripción Electrónicos  Digital Media System-on-Chip (DMSoC)
PDF  163 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TMS320DM355CZCEA13 Datasheet(HTML) 126 Page - Texas Instruments

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PCLK
(PositiveEdgeClocking)
PCLK
(NegativeEdgeClocking)
7,9
HD/VD
CI[7:0]/YI[7:0]/
CCD[13:0]
8,10
11
12
5
6
CAM_WEN_FIELD
PCLK
(PositiveEdgeClocking)
15
16
23
24
CI[7:0]/YI[7:0]/
CCD[13:0]
CAM_WEN_FIELD
PCLK
(PositiveEdgeClocking)
TMS320DM355
SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010
www.ti.com
Figure 5-24. VPFE (CCD) Slave Mode Input Data Timing
Table 5-19. Timing Requirements for VPFE (CCD) Master Mode(1) (see Figure 5-25)
DM355
NO.
PARAMETER
UNIT
MIN
MAX
15
tsu(CCDV-PCLK)
Setup time, CCD valid before PCLK edge
3
ns
16
th(PCLK-CCDV)
Hold time, CCD valid after PCLK edge
2
ns
23
tsu(CAM_WEN_FIELDV-PCLK)
Setup time, CAM_WEN_FIELD valid before PCLK edge
3
ns
24
th(PCLK-CAM_WEN_FIELDV)
Hold time, CAM_WEN_FIELD valid after PCLK edge
2
ns
(1)
The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
Figure 5-25. VPFE (CCD) Master Mode Input Data Timing
126
DM355 Peripheral Information and Electrical Specifications
Copyright © 2007–2010, Texas Instruments Incorporated
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Product Folder Link(s): TMS320DM355



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