L9779WD datasheet(116/170 Pages) STMICROELECTRONICS

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Functional description

L9779WD

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DocID027452 Rev 5

Note:

There is no impact on internal power stages from active pin [WDA] in factory test-mode.

Response comparison

The 2-bit counter <RESP_CNT (1-0)> counts the received bytes of the 32-bit response and

controls the generation of the expected response. Its default value is "11" (corresponds to

"waiting for RESP_BYTE3").

The <RESP_ERR> flag is set '1' when a response byte is incorrect. The flag remains '0' if

the 32-bit response is correct. The ERROR COUNTER is updated with the flag. The default

state of the flag is '0'.

The 2-bit counter <RESP_CNT(1-0)> and the <RESP_ERR> flag are reset to their

corresponding default values at a sequencer-run. The reset condition of the counter

<RESP_CNT (1-0)> and the <RESP_ERR> flag are the corresponding default states.

Procedure of the sequential response comparison:

Table 52. Reset-behaviour of <WDA_INT>, AB1 and <WD_RST>

Signal

Reset source

Reset state

WDA_INT

RST_UV

‘1‘, i.e. pin WDA is active

AB1

RST_UV

‘0‘, i.e. inactive

WD_RST

RST_UV

‘0‘, i.e. inactive

<RESP_CNT(1-0)> = "11": switch the expected response for RESP_BYTE3 to the

comparator

Write access: RESP_BYTE3

Set <RESP_CNT> to "10", update <RESP_ERR> flag

<RESP_CNT(1-0)> = "10": switch the expected response for RESP_BYTE2 to the

comparator

Write access: RESP_BYTE2

set <RESP_CNT> to "01", update <RESP_ERR> flag

<RESP_CNT(1-0)> = "01": switch the expected response for RESP_BYTE1 to the

comparator

Write access: RESP_BYTE1

set <RESP_CNT> to "00", update <RESP_ERR> flag

<RESP_CNT(1-0)> = "00": switch the expected response for RESP_BYTE0 to the

comparator

Write access: RESP_BYTE0

Start sequencer (SEQU_START signal), set <RESP_CNT> to

"11", update <RESP_ERR> flag (update ERROR COUNTER)

Sequencer clears <RESP_ERR> flag to '0

SEQU_START =

(RESP_CNT1) AND RESP_CNT0) AND “response byte write”

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