STK672-442BN-E

No.A2249-13/28

1-7. [Input timing]

The control IC of the driver is equipped with a power on reset function capable of initializing internal IC operations

when power is supplied. A 4V typ setting is used for power on reset. Because the specification for the MOSFET gate

voltage is 5V

5%, conduction of current to output at the time of power on reset adds electromotive stress to the

MOSFET due to lack of gate voltage. To prevent electromotive stress, be sure to set ENABLE=Low while VDD,

which is outside the operating supply voltage, is less than 4.75V.

In addition, if the RESETB terminal is used to initialize output timing, be sure to allow at least 10

s until CLOCK

input.

ENABLE, CLOCK, and RESETB Signals Input Timing

1-8. [Configuration of control block I/O pins]

<Configuration of the MODE1, MODE2, MODE3, CLOCK,

<Configuration of the FAULT2 pin>

CWB, ENABLE, and RESETB input pins>

VDD

VSS

10kΩ

100kΩ

Input pin

VDD

Overcurrent

Overheating

50k

50k

50k

Motor terminal open

Output pin

Pin 8

(The buf fer has an open drain configuration.)

The input pins of this driver all use Schmitt input. Typical specifications at Tc=25

C are given below. Hysteresis voltage

is 0.3V (VIHa-VILa).

Input voltage specifications are as follows.

VIH=2.5Vmin

VIL=0.8Vmax

4Vtyp

3.8Vtyp

At least 10

s

At least 10

s

No time specification

Control IC power (VDD) rising edge

Control IC power on reset

RESETB signal input

ENABLE signal input

CLOCK signal input

VIHa

When rising

When falling

1.5Vtyp

VILa

1.8Vtyp

Input voltage