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PM0056 Datasheet(PDF) 105 Page - STMicroelectronics |
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PM0056 Datasheet(HTML) 105 Page - STMicroelectronics |
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105 / 156 page ![]() DocID15491 Rev 5 105/156 PM0056 Core peripherals 4 Core peripherals 4.1 About the STM32 core peripherals The address map of the Private peripheral bus (PPB) is: In register descriptions: • The required privilege gives the privilege level required to access the register, as follows: 4.2 Memory protection unit (MPU) This section describes the Memory protection unit (MPU) which is implemented in some STM32 microcontrollers. Refer to the corresponding device datasheet to see if the MPU is present in the STM32 type you are using. The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: • Independent attribute settings for each region • Overlapping regions • Export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex- M3 MPU defines: • Eight separate memory regions, 0-7 • A background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. Table 33. STM32 core peripheral register regions Address Core peripheral Description 0xE000E010-0xE000E01F System timer Table 49 on page 154 0xE000E100-0xE000E4EF Nested vectored interrupt controller Table 44 on page 128 0xE000ED00-0xE000ED3F System control block Table 48 on page 149 0xE000ED90-0xE000ED93 Memory protection unit Table 40 on page 117(1) 1. Software can read the MPU Type Register at 0xE000ED90 to test for the presence of a memory protection unit (MPU). 0xE000EF00-0xE000EF03 Nested vectored interrupt controller Table 44 on page 128 Privileged Only privileged software can access the register. Unprivileged Both unprivileged and privileged software can access the register. |
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